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1999 mos integrated circuit pd16364 160-bit high-voltage cmos driver document no. s14000ej2v0ds00 (2nd edition) date published november 2002 ns cp(k) printed in japan data sheet the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. description the pd16364 is a high-voltage cmos driver for el display. it consists of 4 40/8 20-bit data latch, 160-bits data latch, 160-bit level shifter, and a high-voltage cmos driver. the logic circuit operates on 5-v power supply (cmos level input), so that it can be connected to a micro-controller. the driver block is comprised of 60 v, 25 ma max. high-voltage output buffer, and both the logic block and driver block employ a cmos, allowing operation with low power consumption. features ? high-voltage full cmos process ? high-voltage output (60 v, 25 ma max.) ?4 40/8 20-bit data latch (4/8-bit data input) ? high-speed data transfer (f clk = 16 mhz: in cascade connection) ? wide operating temperature range (t a = ? 40 to +85c) ordering information part number package pd16364n - tcp (tab package) remark the tcp?s external shape is customized. to order the required shape, please contact one of our sales representatives. the mark shows major revised points.
data sheet s14000ej2v0ds 2 pd16364 1. block diagram control circuit dst sck eio1 eio2 20/40-bit latch selector 4 x 20/8 x 20-bit data latch 160-bit data latch 20/40 160 160-bit level shifter 160 160-bit high-voltage cmos driver 160 l,/r data mpx 4/8 d 0 d 7 v dd1 v ss1 v dd2 v ss2 out1 out 157 out 158 oc bs rev out 159 out 160 out2 out3 out4 remark /xxx indicates active low si gnal.
data sheet s14000ej2v0ds 3 pd16364 2. pin configuration ( pd16364n-xxx: copper foil surface, face-up) dummy v ss2 v dd2 bs l,/r oc rev dst clk eio1 eio2 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 out1 out2 out3 out4 out5 out157 out158 out159 out160 dummy dummy dummy dummy dummy dummy dummy dummy dummy dummy dummy out156 v dd2 v ss2 v dd2 v dd2 v ss2 v ss2 v ss1 v dd1 copper foil suface remark this figure does not specify the tcp package. caution be sure to use all the v dd1 , v dd2 , v ss1 , and v ss2 pins. keep the v ss1 and v ss2 pins at the same voltage level.
data sheet s14000ej2v0ds 4 pd16364 3. pin functions pin symbol pin name i/o description eio1 enable i/o1 i/o l,/r pin = ?l? level: input l,/r pin = ?h? level: output eio2 enable i/o2 i/o l,/r pin = ?h? level: input l,/r pin = ?l? level: output sck shift clock input input fall edge operation. input shift clock for 4 x 40/8 x 20-bit data latch. dst data strobe input input fall edge operation. data are latched to 160-bits data latch and also set outputs of out1 to out160. d 0 to d 7 data input input data input. when bs is low level, d 4 to d 7 pins should be connected to v ss1 or v dd1 . l,/r select left or right shift input refer to 4.truth table oc output control input when oc pin is low level, output is normal operation. when oc pin is high level, output become low level. rev invert input data input when rev pin is low level, input data d 0 to d 7 are latched without inversion. when rev pin is high level, input data d 0 to d 7 are inverted before latching. bs bus select input when bs pin is low level, data bus is4 bits. when bs pin is high level, data bus is 8 bits. out1 to out160 high-voltage output output output level is v ss2 or v dd2 . these outputs are changed by falling edge of dst pin. v dd1 logic power supply ? logic power supply v dd2 driver power supply ? driver power supply v ss1 logic ground ? grounding v ss2 driver ground ? grounding ! !
data sheet s14000ej2v0ds 5 pd16364 4. truth table shift register block (4 x 40 data latch, bs = l) l,/rsck123...40 d 3 159...157 d 2 2 6 10 ... 158 d 1 3 7 11 ... 159 l level d 0 4 8 12 ... 160 d 3 160 156 152 ... 4 d 2 159 155 151 ... 3 d 1 158 154 150 ... 2 h level d 0 157 153 149 ... 1 shift register block (8 x 20 data latch, bs = h) l,/rsck123...20 d 7 1 9 17 ... 153 d 6 2 10 18 ... 154 d 5 3 11 19 ... 155 d 4 4 12 20 ... 156 d 3 5 13 21 ... 157 d 2 6 14 22 ... 158 d 1 7 15 23 ... 159 l level d 0 8 16 24 ... 160 d 7 160 152 144 ... 8 d 6 159 151 143 ... 7 d 5 158 150 142 ... 6 d 4 157 149 141 ... 5 d 3 156 148 140 ... 4 d 2 155 147 139 ... 3 d 1 154 146 138 ... 2 h level d 0 153 145 137 ... 1 control block l,/r eio1 eio2 h level out in l level in out driver block oc rev dn driver output llll llhh lhlh lhhl h x x l (all driver outputs are l.) !
data sheet s14000ej2v0ds 6 pd16364 5. electrical specifications absolute maximum ratings (t a = 25c, v ss1 = v ss2 = 0 v) parameter symbol rating unit logic part supply voltage v dd1 ?0.5 to +6.0 v driver part supply voltage v dd2 ?0.5 to +60 v logic part input voltage v i1 ?0.5 to v dd1 + 0.5 v logic part output voltage v o1 ?0.5 to v dd1 + 0.5 v driver part output voltage v o2 ?0.5 to v dd2 + 0.5 v logic part output current i o1 10 ma driver part output current i o2 25 ma operating ambient temperature t a ?40 to +85 c storage temperature t stg ?55 to +125 c cautions 1. t a 25c , load should be alleviated at a rate of ?4.5 mw/c. 2. product qualify may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. recommended operating range (t a = ?40 to +85c, v ss1 = v ss2 = 0 v) parameter symbol conditions min. typ. max. unit logic part supply voltage v dd1 4.5 5.0 5.5 v driver part supply voltage v dd2 20 55 v high-level input voltage v ih 0.8 v dd1 v dd1 v low-level input voltage v il 00.2 v dd1 v i ol2 +20 ma driver part output current i oh2 ? 20 ma caution turn of and off power sequence must be as follows: turn-on sequence: v dd1 input v dd2 turn-off sequence: v dd2 input v dd1
data sheet s14000ej2v0ds 7 pd16364 electrical characteristics (t a = ?40 to +85c, v dd1 = 4.5 to 5.5 v, v dd2 = 55 v, v ss1 = v ss2 = 0 v,) parameter symbol conditions min. typ. max. unit v oh1 logic, i oh1 = ? 0.4 ma, v dd1 ? 0.4 v high-level output voltage v oh2 out1 to out160, i oh2 = ? 1.0 ma v dd2 ? 0.4 v v ol1 logic, i ol1 = 0.4 ma 0.4 v low-level output voltage v ol2 out1 to out160, i ol2 = 1.0 ma 0.4 v high-level input current i ih v i = v dd1 5.0 a low-level input current i il v i = 0 v ? 5.0 a high-level input voltage v ih logic 0.8 v dd1 v low-level input voltage v il logic 0.2 v dd1 v r on variance r var out1 to out160 (in one chip under constant t j note1 ) 30 % logic part dynamic current consumption i dd1 note2 10 ma driver part dynamic current consumption i dd2 note2 10 ma standby current i standby note3 500 a notes 1. r var = (1 ? xn/x avg ) x 100 xn = impedance of outn, x avg = impedance of average i oh2 = ? 1.0 ma, i ol2 = 1.0 ma 2. f sck = 16 mhz, f dst = 36 khz, v in = v dd1 or v ss1 , no load 3. v in = v dd1 or v ss1 , no load switching characteristics (t a = ?40 to +85c, v dd1 = 4.5 to 5.5 v, v dd2 = 55 v, v ss1 = v ss2 = 0 v) parameter symbol conditions min. typ. max. unit t plh1 dst eion , c l = 30 pf 70 ns enable pulse delay time t phl2 last sck eion , c l = 30 pf 40 ns t phl3 7 s driver output delay time t plh3 dst out1 to out160, c l = 2000 pf 7 s input capacitance c i 20 pf
data sheet s14000ej2v0ds 8 pd16364 timing requirement (t a = ?40 to +85c, v dd1 = 4.5 to 5.5 v, v dd2 = 55 v, v ss1 = v ss2 = 0 v, t r = t f = 13.0 ns) parameter symbol conditions min. typ. max. unit sck cycle time t csck 62 ns sck pulse width pw clk 20 ns dst cycle time t cdst 1000 ns dst high-level pulse width pw dst 30 ns dst-sck time t dst-sck dst 1st sck 100 ns sck-dst time t sck-dst last sck dst 30 ns data setup time t setup 20 ns data hold time t hold 20 ns rev setup time t rsetup 40 ns rev hold time t rhold 30 ns eio-sck time1 t eio-sck1 eion 1st sck 22 ns eio-sck time2 t eio-sck2 eion 1st sck 25 ns
data sheet s14000ej2v0ds 9 pd16364 switching characteristics and timing requirements waveform timing requirement waveform 0.8 v dd1 output 0.2 v dd1 0.8 v dd1 or 0.8 v dd2 0.2 v dd1 or 0.2 v dd2 input switching characteristics waveform t rhold t rsetup t phl3, , t plh3 pw clk t csck t r t sck-dst t hold t setup t f last t dst-sck sck dst d 0 to d 7 out (n) rev t r t f t eio-sck1 t phl2 t plh1 1 21 dst sck eio (output) eio (input) pw clk pw dst t dst-sck 40/20 t eio-sck2 t cdst
data sheet s14000ej2v0ds 10 pd16364 timing example (640 dots x 3/line, bs = h, l,/r = h) sck out1- out160 d 0 to d 7 ic1 eio2 1 23 20 1 23 20 1 23 20 1 23 20 1 2 dst ic1 eio1 / ic1 eio2 ic2 eio1 / ic3 eio2 ic11 eio1 / ic12 eio2 ic1 data reading ic2 data reading ic3 data reading ic12 data reading
data sheet s14000ej2v0ds 11 pd16364 6. recommended soldering conditions the following conditions must be met for soldering conditions of the pd16364. for more details, refer to the semiconductor device mounting technology manual (c10535e). please consult with our sales offices in case other soldering process is used, or in case the soldering is done under different conditions. pd16364n- : tcp (tab package) mounting condition mounting method condition soldering heating tool 300 to 350c: heating for 2 to 3 seconds: pressure 100g (per solder) thermocompression acf (adhesive conductive film) temporary bonding 70 to 100c: pressure 3 to 8 kg/cm 2 : time 3 to 5 seconds. real bonding 165 to 180c: pressure 25 to 45 kg/cm 2 : time 30 to 40 seconds. (when using the anisotropy conductive film sumizac1003 of sumitomo bakelite, ltd.) caution to find out the detailed conditions for packaging the acf part, please contact the acf manufacturing company. be sure to avoid using two or more packaging methods at a time.
data sheet s14000ej2v0ds 12 pd16364 [memo]
data sheet s14000ej2v0ds 13 pd16364 [memo]
data sheet s14000ej2v0ds 14 pd16364 [memo]
data sheet s14000ej2v0ds 15 pd16364 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
pd16364 reference documents nec semiconductor device reliability/quality control system (c10983e) semiconductor device mounting technology (c10535e) the information in this document is current as of november, 2002. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec electronics data sheets or data books, etc., for the most up-to-date specifications of nec electronics products. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec electronics. nec electronics assumes no responsibility for any errors that may appear in this document. nec electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec electronics products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec electronics or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. nec electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec electronics endeavors to enhance the quality, reliability and safety of nec electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. nec electronics products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to nec electronics products developed based on a customer- designated "quality assurance program" for a specific application. the recommended applications of an nec electronics product depend on its quality grade, as indicated below. customers must check the quality grade of each nec electronics product before using it in a particular application. "standard": computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of nec electronics products is "standard" unless otherwise expressly specified in nec electronics data sheets or data books, etc. if customers wish to use nec electronics products in applications not intended by nec electronics, they must contact an nec electronics sales representative in advance to determine nec electronics' willingness to support a given application. (note) (1) "nec electronics" as used in this statement means nec electronics corporation and also includes its majority-owned subsidiaries. (2) "nec electronics products" means any product developed or manufactured by or for nec electronics (as defined above). ? ? ? ? ? ?

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